A semiconductor manufacturing test process commonly has a burn-in test processing step. A burn-in test stresses integrated circuits (ICs) at higher temperatures (e.g., 125° C.) for several hours in an effort to damage weak memory cells. A burn-in test is typically performed on ICs after the ICs have been packaged.
Some ICs have been manufactured to include redundant elements. A redundant element includes identical memory cells grouped in either a word line (WL) or a bit line (BL). In another words, one primary element on an IC could have one or more redundant elements that are identical to the primary element. If during a test process, the primary element fails, redundant elements that do not fail the test can be used in place of the primary element. Historically, implementing redundancy repairs could only occur prior to packaging, while the ICs were still on a wafer.
Recent developments in semiconductor manufacturing, like electronic fuses and wafer scale packages, make it possible to now perform repairs after the IC is packaged. Therefore, repairs after burn-in can be made to improve the yield of ICs.